1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and a control method thereof, and more specifically, to a semiconductor integrated circuit provided with a circuit for saving and recovering an internal state and a control method thereof.
2. Description of Related Art
Semiconductor integrated circuits provided with a low power consumption function such as a standby function and a resume function have attracted attention in recent years. In the stop of power supply, the internal node data of a semiconductor integrated circuit is generally deleted excluding a data stored in a nonvolatile memory. Accordingly, the internal node data needs to be set in the semiconductor integrated circuit in order to restart an operation from a state immediately before the stop of the power supply, upon the restart of the power supply.
According to Japanese Laid Open Patent Application (JP-A-Heisei 6-52070), an integrated circuit is disclosed in which the internal node data held by registers in the integrated circuit is saved in an external memory when the power supply is stopped. This integrated circuit includes the registers, a data saving unit, and a data recovering unit. The registers are connected to form a scan chain, the data saving unit makes the registers to form the scan chain in response to an external signal in a data saving mode such that the data held the registers are outputted to an external unit via the formed scan chain. At this time, the data saving unit serial/parallel-converts the internal node data into a data of a predetermined bit width and stores in a memory through a data input/output unit. The data recovering unit makes the registers to form the scan chain in response to an external signal in a data recovering mode, and recovers the saved data into the original registers via the formed scan chain. At this time, the data recovering unit uses a data input/output section to convert the internal node data read out from the memory, where the data with a predetermined bit width is converted into serial internal node data, which is returned through the scan chains.
Moreover, according to Japanese Laid Open Patent application (JP-P-2004-164647A), a data processing apparatus is disclosed which is provided with a circuit having one or more nodes, a memory, a system bus, and a state storage controller. The circuit is used for data processing, and stores one or more data values to define a state of the circuit entirely. The memory stores data. The system bus is connected to the circuit and the memory, and transfers multi-bit data words between the circuit and the memory in response to a memory transfer request given to the system bus during a normal operation to the circuit and the memory. The state storage controller is connected to the circuit and the system bus, and sequences of memory write requests are generated on the system bus in response to storage triggers by reading data values to define a state of the circuit from the one or the plurality of the nodes, and one or a plurality of state storage multi-bit data languages to express the data values is written in the memory, so that a state of the circuit can be retrieved by using the one or the plurality of the state storage multi-bit data languages. As related techniques, there is a technique described in U.S. patent application No. 2005/0149799.
Moreover, according to Japanese Laid Open Patent application (JP-P-2002-196846A), a technique is described for facilitating a saving operation of data which is not mapped into an address of a CPU. The CPU performs a simple switching process without a special switching process to achieve saving and recovery of the data. An LSI chip is divided into two regions of a main power supply region and a backup power supply
An internal state in semiconductor integrated circuits is thus saved and retrieved by using the scan chains so that functions such as standby and resume can be realized. However, when the scan chains are operated, entire flip-flops to compose the scan chains are supposed to have simultaneous shift operations. In normal operations, only about a half to one third of a clock signal is supplied to built-in flip-flops by clock signal gating, where the flip-flops are controlled so as not to perform unnecessary operations. Accordingly, if a clock signal is supplied to the entire flip-flops which thereby operate simultaneously, a rapid current flow causes generation of a so-called IR drop which mean a voltage decrease by a resistive component of wiring, leaving a possibility of malfunctions.